Hyderabad
Founded by highly respected Silicon Valley veterans – with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore
Our pay comprehensively beats “ALL” Semiconductor product players in the Indian market
PCIe / CXL Verification Lead
Experience: 10+ years in Design Verification (3–4+ years specifically in PCIe/CXL)
Role Overview
We are looking for a highly experienced Verification Lead to drive the verification of high-performance PCIe Gen5/Gen6 and CXL 2.0/3.x controller IPs or subsystems.
The candidate will be responsible for defining the verification strategy and executing the verification plan to ensure protocol compliance, architectural integrity, and system-level robustness for next-generation data center and AI accelerator platforms.
Key Responsibilities
- Lead end-to-end verification of PCIe Gen5/6 and CXL 2.0/3.x controller IP or subsystem
- Define verification strategy, test plans, coverage metrics, and sign-off criteria
- Develop and own SystemVerilog/UVM-based verification environments
- Debug LTSSM state transitions, link training, ordering rules, flow control, and error handling
- Work closely with RTL, architecture, and SoC integration teams
- Integrate PCIe/CXL subsystems into SoC or FPGA platforms
- Analyze latency, bandwidth, compliance, interoperability, and performance metrics
- Drive protocol compliance and system-level validation
Minimum Qualifications
- BE/BTech with 10+ years OR ME/MTech with 8+ years in Electrical / Computer Engineering
- Strong hands-on expertise in SystemVerilog, UVM, and Object-Oriented Programming
- 3–4+ years of hands-on experience validating PCIe Gen5/Gen6 or CXL 1.1 / 2.0 on ASIC or FPGA
- Proven experience building verification environments from scratch
- Experience defining test plans and driving tape-out sign-off
- Experience in integration and verification of complex system-level IP features
- Strong collaboration experience with RTL and SoC teams
- Good understanding of memory protocols (DDR / ONFI / NAND / SPI / QSPI / Flash)
- Proficiency with AXI / CHI or similar interconnect protocols
- Familiarity with scripting languages (Perl / Python or similar)
- Excellent communication, analytical, and debugging skills
Preferred Qualifications
- Exposure to CXL.cache and CXL.mem coherency and memory expansion flows
- Understanding of DDR / HBM / Flash / CXL-attached memory systems
- Knowledge of SoC boot flows involving processors
- Experience with FPGA setup and simulation
- Exposure to Gate-Level Simulation (GLS)
- Strong understanding of PCIe/CXL Physical, Link, and Transaction layers
- Experience with PCIe/CXL compliance testing (Endpoint or Root Port)
- Ability to analyze PCIe/CXL performance metrics
- Experience in system-level verification for PCIe/CXL-based systems
Contact: Uday
Mulya Technologies
Email:
…