Lead STA Engineer

ACL Digital is Hiring for STA Engineers for Bangalore location.

Exp: 5+Years

Key Responsibilities:

Perform block-level and full-chip Static Timing Analysis (STA)

Develop and maintain SDC timing constraints (clocks, IOs, false paths, multicycle paths)

Collaborate with PD, CTS, and Design teams for timing closure

Handle ECO timing fixes and timing signoff

Perform low power timing checks using UPF/CPF

Required Skills:

• Hands-on experience with PrimeTime / Tempus
• Strong expertise in SDC constraints & timing concepts
• Experience with multi-clock designs
• Knowledge of OCV/AOCV/POCV
• Understanding of digital & physical design flow

Looking for Lesser notice Period.

Kindly reach out to me on

Regards,

Sruthi.

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