DFT Expert

We are currently seeking a highly skilled engineer to enhance the testability and reliability of our ASIC designs.

• Hands-on experience in scan-stitching concepts, specifically for ATPG tools is essential.
• A solid understanding of advanced pattern generation techniques, as well as debug methodologies, is required.
• Familiarity with Tessent ATPG and SpyGlass-DFT for rule checks and analysis is necessary.

This role will focus on developing effective solutions to improve test coverage, reduce DRC violations, and optimize overall silicon testability. We’re looking for someone who can drive innovation and achieve robust coverage closure.

…