TITLE: Senior ASIC / RTL / Logic Design Engineer – Memory Controller Design
LOCATION: GREATER HYDERABAD AREA
ABOUT COMPANY:
Founded by highly respected Silicon Valley veterans, we are a startup headquartered in US with its design centre established in Santa Clara, California. / Hyderabad/ Bangalore
JOB DESCRIPTION:
We are seeking a highly experienced, innovative, and technically strong ASIC / RTL / Logic Design Engineer to join our Memory Controller Design Centre of Excellence (CoE). This role offers the opportunity to architect and implement high‑performance memory controller IP for cutting‑edge AI compute platforms powering large‑scale data centers and advanced machine‑learning workloads.
Responsibilities
- Design and deliver standards‑compliant, production‑ready IP blocks for DDR5, HBM4, and LPDDR6 memory controllers, optimized for AI‑centric server SoCs operating at 9600 Mbps to 14400 Mbps and beyond.
- Develop architecture, micro‑architecture, and detailed design specifications tailored for AI compute workloads, ensuring best‑in‑class performance, power efficiency, and area (PPA).
- Enhance ASIC development flows using advanced EDA tools, automation, and scripting (Python, Perl, TCL) to support rapid iteration cycles for AI‑focused silicon.
- Implement complex RTL design blocks in Verilog/SystemVerilog, following robust design methodologies suitable for high‑bandwidth, low‑latency AI accelerators.
- Perform functional simulation, performance modeling, and debug to validate correctness and throughput under AI‑oriented traffic patterns.
- Demonstrate strong understanding of Lint, CDC, Synthesis, Power Analysis, STA constraints, and LEC for high‑frequency, high‑reliability server‑class designs.
- Define and optimize timing constraints to meet aggressive frequency targets typical of AI compute architectures.
- Identify, track, and resolve design bugs across the development lifecycle using industry‑standard tracking systems.
- Collaborate closely with verification, physical design, architecture, and firmware teams to ensure seamless integration into AI‑centric server chip platforms.
- Participate in design reviews, code reviews, and technical discussions, driving continuous improvement in design quality and methodology.
- Mentor junior engineers, fostering a culture of technical depth, innovation, and excellence.
Key Qualifications
- B.E / M.Tech / Ph.D. in Electrical Engineering, Electronics, VLSI, or related field from a reputed institution.
- 10+ years of hands‑on experience in ASIC design, RTL development, and logic design for complex SoCs or IP subsystems.
- Strong expertise in Verilog and SystemVerilog, with deep knowledge of digital design fundamentals, memory subsystems, and high‑speed interfaces.
- Proven experience with Lint, CDC, Synthesis, Power Analysis, STA, and LEC tools (Synopsys, Cadence, Mentor).
- Experience working on server‑class, high‑performance, or AI‑accelerator SoCs is a strong plus.
- Excellent analytical, debugging, and problem‑solving skills with the ability to thrive in a fast‑paced, product‑focused environment.
- Strong communication and collaboration skills for working with cross‑functional global engineering teams.
Contact: Uday
muday_bhaskar@yahoo.com
Mulya Technologies
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