Job Title: Physical Design EM/IR/ESD Lead
Location: Bengaluru, India Experience: 10–15 years Industry: Semiconductors | AI | Networking | ASIC Design
Role Overview
As the Physical Design EM/IR/ESD Lead you will be the ultimate guardian of our
silicon reliability and power integrity. In the high-stakes world of AI SOCs, power delivery is the
heartbeat of the chip. You will hold end-to-end ownership of the EM/IR and ESD strategy,
bridging the gap between ambitious architectural power demands and robust, manufacturable
physical implementation. This is a leadership role designed for an expert who thrives on defining
methodologies from scratch and ensuring first-pass silicon success.
Key Responsibilities
Methodology & Flow Development
● Define & Own EM/IR/ESD Flow: Design, develop, and maintain a robust, automated,
and scalable physical design flow for Electromigration (EM), Static/Dynamic IR-Drop (IR),
and ESD analysis.
● PDN Leadership: Lead the definition of the SoC-level Power Distribution Network
(PDN) architecture. Drive partition-level teams to meet aggressive IR-drop and power
integrity specifications.
● ESD/LUP Strategy: Collaborate with integration and floorplanning teams to implement
essential ESD and Latch-Up protection elements (HBM, CDM) across the chip.
● Advanced Sign-off: Develop innovative methodologies to enhance accuracy and
reduce Turn-Around-Time (TAT) for reliability sign-off.
Tool Expertise & Vendor Collaboration
● Evaluation & Benchmarking: Lead the selection and deployment of best-in-class EDA
tools (e.g., Ansys RedHawk SC, Cadence Voltus, Calibre PERC).
● Vendor Engagement: Serve as the primary technical interface with EDA vendors,
driving feature enhancements and influencing tool roadmaps to meet project-critical
requirements.
Technical Leadership & Support
● Subject Matter Expertise: Act as the SME for all reliability aspects, providing
expert-level support on complex sign-off challenges and final tape-out criteria.
● Cross-Functional Synergy: Partner with Foundry teams to incorporate
technology-specific rules and with Device/Layout teams to optimize protection structures.
Key Skills & Technical Requirements
● EM/IR Sign-off Mastery: Expert proficiency in analyzing static/dynamic IR-drop and
identifying EM violations on advanced nodes.
● Tool Proficiency: High proficiency with Ansys RedHawk SC and/or Cadence Voltus.
● ESD/LUP Excellence: Mastery of ESD/Latch-Up protection concepts and sign-off
procedures using Calibre PERC.
● Physical Design Fundamentals: Deep understanding of floorplanning, power grid mesh
creation, P&R, and timing analysis.
● Scripting & Automation: Expert-level proficiency in Python, Tcl, or Perl is essential for
building and automating custom flows.
Background & Qualifications
● Education: Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a
related field.
● Experience: 10–15 years in VLSI physical design, with a dedicated focus on power
integrity and reliability.
● Process Technology: Proven track record on advanced process nodes (7nm, 5nm,
and below) is highly desirable.
● Soft Skills: Exceptional analytical debugging skills and the ability to articulate complex
sign-off statuses to cross-functional stakeholders.
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