Fpga design

FPGA design & prototyping EngineersExperience – 5-6 yearsLocation : Hyderabadusing Cadence/Synopsys/Vivado flows.Strong RTL(verilog/system verilog) skills with experience in IP development.– Ability to verify designs by writing simple testbenches.– Strong foundation in logic synthesis and timing closure concepts.– Good knowledge of So C architecture, AXI bus protocols, hardware debug.– Experience of working with Xilinx FPGAs, Vivado tool flows and micro architecture development is a plus.Interested,please share your updated resume to…