Company:
QualcommIndia Private Limited
JobArea:
Engineering Group, Engineering Group >HardwareEngineering
GeneralSummary:
Qualcomm’sBangalore WLAN PHY (Baseband) team is seeking VLSI (SrStaff)Digital Design Engineers to lead IP development for thelatest WiFi standards.
OurWLAN PHY team, comprised of highly passionate and seasoned domainexperts, prides itself on years of experience in taking WLAN PHYdesigns from concept to siliconindependently.
WLAN PHY teamis responsible for delivering the end-to-end Tx/Rx DSP chains – allthe way from antenna samples post ADC to raw bits for upper layersand on the reverse path from raw bits to DAC. The team specializesin working with challenges of practical high-speed wirelesscommunication systems and finding innovative solutions to counterthem.
The team worksextensively on typical signal processing functions like filters,matrix transformations (e.g.: QR, Cholesky decomposition), channelestimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.:LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, andcontributes to the development/ enhancement/ evaluation of signalprocessing algorithms to cater to newrequirements.
We are lookingfor someone as passionate as us and takes pride in theirwork.
WiFi’s ubiquity inmodern times is undeniable, and the IEEE 802.11 Working Group iscontinually developing new standards to satisfy the growing demandfor high throughput and low-latency real-time applications, such asVR and AR.
Qualcomm is atthe forefront of the WiFi revolution, aiming to become the globalleader in WiFi chip solutions. The WLAN PHY team in Bangalore isinstrumental in realizing thisvision.
Requirements:
Lookingfor a candidate with 12 to 20 years of hands-on experience inmicro-architecting and developing complexIPs.
Expertise in digitaldesign, VLSI concepts, and experience in creatingpower/area-efficient IPs across multiple clock domains areessential.
Proficiency inRTL coding and familiarity with RTL QA flows such as PLDRC, CDC,and CLP (optional) isexpected.
Candidates shouldbe capable of proposing design alternatives to meetarea/power/performance specifications and presenting these optionsfor review.
Experience inleading, guiding, or managing junior team members isadvantageous.
Repeatedsuccess in taking IP designs from requirements to silicon isrequired.
While notmandatory, having developed IPs for wireless technologies (WLAN,LTE, NR, BT, UWB, etc.) or past HLS experience would bebeneficial.
Skills:
Musthave: Proficient in Verilog RTL coding, uArch, CDCcheck, PLDRC, Timing constraints, Python/Perl. Experience indesign/debugging complex data-path/control-path IPs. Goodcommunication, analytical & leadershipskills.
Good tohave: System Verilog, Visio, Knowledge of signalprocessing concepts/algorithms and Wi-Fi standards(802.11a/b/g/n/ac/ax), experiencewith
MinimumQualifications:
• Bachelor’s degree inComputer Science, Electrical/Electronics Engineering, Engineering,or related field and 6+ years of Hardware Engineering or relatedwork experience. ORMaster’s degree in ComputerScience, Electrical/Electronics Engineering, Engineering, orrelated field and 5+ years of Hardware Engineering or related workexperience. ORPhD in Computer Science,Electrical/Electronics Engineering, Engineering, or related fieldand 4+ years of Hardware Engineering or related workexperience.
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