Lead DFT Engineer | Hyderabad / Bangalore
We are looking for an experienced Lead DFT Engineer with strong expertise in DFT implementation, Scan architecture, and ATPG using Tetramax / DFT Max tools.
Location: Hyderabad / Bangalore
Experience: 8 – 12 Years
⏳ Notice Period: Immediate to 30 Days Preferred
Key Skills
Design For Test (DFT) Implementation
Scan Insertion & Scan Compression
ATPG using Tetramax
Synopsys DFT Max
Stuck-at / Transition / Path Delay Faults
JTAG / Boundary Scan
MBIST / LBIST Concepts
ASIC / SoC Design Flow
Responsibilities
Lead DFT architecture and implementation for complex SoC designs
Perform scan insertion and ATPG pattern generation
Achieve high fault coverage and test optimization
Work closely with RTL, PD, and Verification teams
Support silicon bring-up and test debugging
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